A market of an electronic commerce service via the Internet such as e-commerce and net banking has steadily expanded. Also, an electronic money service using an IC card has entered into spread/expansion period. And, in these services, a higher-leveled security technique is always demanded.
In a software level, sufficient security has been achieved by an encryption technique with a central focus on strong encryption algorithm. On the other hand, in a hardware level on which the similar algorithm is physically implemented, it has been pointed out that there is a possibility of allowing an attacker such as a hacker (cracker) to decipher a secret key.
Conventionally, a method of storing an ID at manufacturing by using Fuse or a non-volatile memory has been used. These techniques are described in “ID Identification Circuit using Device Mismatch, K. Lofstrom, et al., ISSCC2000” (Non-Patent Document 1) and “A 1.6 pJ/bit 96% Stable Chip-ID Generating Circuit using Process Variations, Y. Su, et al., ISSCC2007” (Non-Patent Document 2).
FIGS. 1A and 1B are conceptual diagrams for describing an operation of Non-Patent Document 1. Also, FIG. 2 is a diagram in a case that the technique of Non-Patent Document 1 is practically applied to inspection of a cell array.
FIG. 1A shows that a comparator 9001s is used for inspecting a transistor array 9003s included in a cell array 9003.
Each of transistors T1, T2, T3, . . . , Tn in the transistor array 9003s has a different threshold voltage from each other. These threshold voltages are different among products at the manufacturing stage, and are unique for each chip.
By an address decoder 9004, a transistor accessed in each cycle is switched. In this manner, an intermediate potential V1 between a resistor 9002s and the transistor array 9003s is changed in accordance with operations of the transistors. As described above, the threshold voltage of each transistor varies for each product. Therefore, the intermediate potential V1 is changed due to random variations.
FIG. 1B is a diagram showing a correspondence between the intermediate potential V1 and an ID which is a comparator output. As showed in the figure, output values of an N cycle and an (N−1) cycle are compared with each other for conversion from an analog value to a digital value, so that a chip-unique data column (chip-unique ID) is generated.
By comparing the generated data column and a chip-unique ID previously stored in a database at the manufacturing, the ID is verified.
FIG. 2 shows a structure including the address decoder 9004 at generating the unique ID for the cell array 9003 in FIGS. 1A and 1B.
FIG. 3 is a conceptual diagram for describing an operation of Non-Patent Document 2.
In a method of Non-Patent Document 2, the chip-unique ID is generated by using a cross-coupled NOR. Similarly to the transistors T1, T2, T3, . . . , Tn in FIG. 1A, each of threshold voltages of transistors M0 to M9 in this figure is also different for each cell. Further, by the threshold voltages of the transistors M0 to M9 in this figure, a value (V0, V1) stored in each cell is determined.
Similarly to a method of Non-Patent Document 1, by switching a cell accessed in each cycle, the data column of the chip-unique ID is generated. In the technique described in Non-Patent Document 2, the data column of the chip-unique ID is generated by using a cross-coupled converter, and therefore, the technique is different from that of Non-Patent Document 1, and has a feature that an amplifier with a low offset is not required.